1. Field of the Invention
This invention relates to a photo-electric conversion circuit utilizing a photodiode, which can be effectively incorporated, for instance, in the photometric circuit of a camera.
2. Background of the Invention
A variety of photo-electric conversion circuits, which form a part of the photometric circuit of a camera, have been proposed in the art. One example of the photo-electric conversion circuits is as shown in FIG. 1.
In the conventional circuit of FIG. 1, a photodiode 1 is connected between the gate and the source of FET (field-effect transistor) 3 which forms a source follower circuit with a resistor 2. The gate of the FET 3 is connected to the collector of a compression transistor 4. A high input impedance circuit made up of the FET 3, an output transistor 5 and exposure factor setting variable resistors 6 and 7 is connected between the base and the collector of the gate drive transistor 4 so that the compression transistor 4 performs a compression action on the photo-electric conversion voltage.
The output transistor 5 in the feedback circuit is driven by a constant current on the constant current action of a transistor 10 which is biased by an FET 8 and a diode-connected transistor 9. Therefore the variable resistors 6 and 7 show linear resistance.
In the above-described photo-electric conversion circuit, the photodiode 1 is negative-biased by a reverse voltage at all times. Its photocurrent flows into the compression transistor 4, so that a compression voltage E.sub.1 is developed between the base and the emitter of the compression transistor 4. The compression voltage E.sub.1 corresponds to the APEX data of an object's luminance.
The compression voltage E.sub.1 is added to the terminal voltage E.sub.2 and E.sub.3 across the variable resistors 6 and 7 which are determined according to exposure factors such as for instance a film sensitivity. This voltage sum (E.sub.1 +E.sub.2 +E.sub.3) is applied to an output line 11.
The above-described photo-electric conversion circuit has been disclosed in Japanese Patent Application Publication No. 22167/1984, U.S. Pat. Nos. 4,106,035 and 4,180,310 corresponding to the Japanese application.
The above-described conventional photo-electric conversion circuit has problems to be solved with respect to the following two points.
(1) Since the photodiode 1 is negative-biased by the predetermined voltage at all times, it can be estimated that the photodiode has an inherent junction capacitance of the order of 300 pF to 600 pF. Therefore, it takes a relatively long period of time for the photodiode to start its normal operation. That is, the response speed of the photodiode is low.
In general, in the case where a photodiode is used as a photo cell, it is preferable that the anode and the cathode are maintained with equal potentials. That is, the photodiode is used in the short-circuit state.
(2) It is desirable that the feedback circuit is a high input impedance circuit whose gain is about one (1). However, in the above-described photo-electric conversion circuit, the gain is liable to decrease because the variations of the compression voltage E.sub.1 and of the terminal voltages E.sub.2 and E.sub.3 of the variable resistors 6 and 7 are fed back to the drain-source voltage V.sub.DS of the FET 3. As a result, the junction capacitance of the photodiode has a stronger effect on the operation.
The above-described gain problem concerns the junction capacitance and the grounding capacitance of the FET. However, in practice, these capacitances are so small that they can be disregarded. Thus, the problem mainly affects the junction capacitance of the photodiode 1. The reduction of the response speed due to the junction capacitance is significant especially when the power switch is turned on.